The disclosed embodiments of the present invention relate to generating an output clock according to a reference clock, and more particularly, to a frequency synthesizer with injection pulling/pushing suppression/mitigation and a related frequency synthesizing method thereof.
Frequency synthesizers are commonly used in a variety of electronic devices. Taking a conventional wireless communications system for example, a radio-frequency (RF) phase-locked loop (PLL) may be used as a frequency synthesizer to generate an RF clock to a following transmitter component according to a baseband reference clock. However, due to certain factors, the RF PLL may suffer from injection pulling/pushing to generate a disturbed RF clock. For one example, concerning the same transceiver, the RF PLL and a power amplifier (PA) may be placed in locations close to each other. As a result, the high-power RF signal generated from the PA may be injected into a controllable oscillator of the RF PLL, thus interfering with the clock frequency of the RF clock generated from the RF PLL. For another example, concerning a case where an electronic device employs a multi-RF design such as DSDA (Dual SIM Dual Active), carrier aggregation (CA), or IDC (In-Device Coexistence), multiple RF systems may be placed in locations close to each other. As a result, the output signal generated from at least one of the RF PLL and the PA of a second RF system may be injected into a controllable oscillator of the RF PLL in a first RF system, thus interfering with the clock frequency of the RF clock generated from the RF PLL in the first RF system.